1. Field of the Invention
The present invention relates to an interface circuit.
2. Description of the Related Art
In general, between circuits with different functions, such as between a memory and a memory control circuit or between a motor driving circuit and a microcomputer, logic level data is transmitted/received to perform predetermined processing. For example, a memory control circuit changes a logic level of an access signal on the basis of an access request from a processor, to perform memory access. Therefore, if the logic level of the access signal is changed by a noise or the like, the memory control circuit may not be able to perform access normally. Thus, some memory control circuits add parity bits to data in the access signals to detect whether or not the memory access is normal (See Japanese Patent Laid-Open Publication NO. 8-16487, for example). Specifically, such memory control circuit adds a parity bit to inputted data and writes the data added with the parity bit into the memory based on a writing instruction from the processor. The memory control circuit also reads the data added with the parity bit from the memory on the basis of a reading instruction from the processor. Then, the memory control circuit detects whether or not the memory access is normal by inspecting the parity bit.
As mentioned above, if a parity bit is added to data to be transmitted/received between the memory and the memory control circuit, for example, it becomes possible to detect whether or not there is an error in the data by inspecting the parity bit. However, if a parity bit is added to the data to be transmitted/received, the amount of the data to be transmitted/received between the memory and the memory control circuit is increased, which is a problem.